IBM unveils a revolution: chips with transistors under 1 nm — a new milestone in microelectronics
IBM is once again asserting itself as a leader in semiconductor technology, unveiling an innovative transistor architecture with a size of just 0.7 nm, equivalent to 7 angstroms. This is not just a step forward—it is a qualitative leap that redefines the boundaries of what is possible in microelectronics.
The key feature of the new technology is the so-called "nanostack." Unlike traditional planar structures, transistors here are arranged in multiple layers, which radically increases the packing density. According to IBM estimates, nearly 100 billion transistors can now be placed on a chip the size of a human fingernail. For comparison, this is several times higher than the figures of even the most advanced 2-nm solutions introduced by the company in 2021.
The expected benefits are impressive: compared to 2-nm technology, the performance of the new chips could increase by 50%, and energy efficiency by as much as 70%. This means not only faster computations but also a significant reduction in power consumption, which is critical for data centers, mobile devices, and artificial intelligence systems.
However, commercial implementation is still some time away. IBM predicts that mass production of chips using 0.7-nm technology will begin no earlier than five years from now. This timeline is tied to the need to adapt manufacturing facilities and address engineering challenges, such as managing heat dissipation and ensuring yield rates.
Analytical commentary: IBM's achievement is an important signal for the entire industry. While competitors like TSMC and Samsung are struggling to master 3-nm and 2-nm processes, IBM is already looking a decade ahead. However, it is worth remembering that this is still a laboratory prototype. The real transition to sub-nanometer structures will require not only time but also enormous investments in retooling factories. Nevertheless, if the stated characteristics are confirmed, we stand on the threshold of an era where chip performance will no longer be a bottleneck for the development of AI and high-performance computing.