Crypto news

IBM has taken a significant step in the development of semiconductor technologies by announcing a new transistor architecture with a size of 0.7 nm (7 angstroms). This challenges the current physical limitations of silicon chips and paves the way for the next generation of computing systems.

The key innovation lies in the transition from the traditional planar arrangement of transistors to a multilayer structure called "nanostack." Instead of placing elements only on the surface of a silicon wafer, IBM proposes stacking them in several vertical layers. This allows for a radical increase in the density of logic elements: according to the company's estimates, up to 100 billion transistors could be placed on an area the size of a fingernail.

Scaling Performance and Energy Efficiency

Comparing the new technology with its own 2nm process from 2021, IBM claims a potential performance increase of up to 50% or an improvement in energy efficiency of up to 70%. These figures are achieved by reducing the distance between transistors and lowering parasitic capacitances. However, commercial implementation of the technology is not expected for at least five years — the standard timeframe for transitioning from a laboratory prototype to industrial production.

Analytical commentary: While 0.7 nm sounds like another marketing label — in reality, it is not the physical gate width but a conventional designation for the process node — the multilayer approach itself does address one of the main challenges of modern microelectronics: the impossibility of endlessly shrinking elements on a plane. If IBM succeeds in scaling the nanostack, it could become the first real step toward chips with a three-dimensional architecture that might one day replace traditional FinFET and GAAFET technologies. However, the industry will have to solve enormous challenges related to heat dissipation and interconnects — otherwise, the nanostack risks remaining just a beautiful theory.